Memory cells of a dynamic random access memory (DRAM) generally comprise a storage capacitor for storing an electrical charge which represents information to be stored, and an access transistor connected to the storage capacitor. The access transistor comprises first and a second source/drain regions, a channel connecting the first and second source/drain regions, and a gate electrode controlling an electrical current flowing between the first and second source/drain regions. The transistor usually is at least partially formed in a semiconductor substrate. The portion in which the transistor is formed generally is denoted as the active area. The gate electrode forms part of a word line, and the gate electrode is electrically isolated from the channel by a gate dielectric. By addressing the access transistor via the corresponding word line, the information stored in the storage capacitor is read out. In particular, the information is read out to a corresponding bit line via a bit line contact.
In currently-used DRAM memory cells, the storage capacitor can be implemented as a trench capacitor in which the two capacitor electrodes are disposed in a trench which extends into the substrate in a direction perpendicular to the substrate surface. According to another implementation of a DRAM memory cell, the electrical charge is stored in a stacked capacitor, which is formed above the surface of the substrate.
Generally, a DRAM memory cell array having a higher packaging density is desirable. For example U.S. Pat. No. 6,419,948, the disclosure of which is incorporated herein by reference in its entirety, discloses a memory cell array in which the active area is formed as a continuous line. The active area line and the bit line are formed as waving lines, so that one bit line and one corresponding active area line intersect at many points. According to this layout, the memory cells can have an area of about 6 F2, wherein F denotes the minimum pitch according to the technology used.
In addition, U.S. Pat. No. 6,545,904, the disclosure of which is incorporated herein by reference in its entirety, discloses a memory cell including an access transistor and a storage capacitor which can be formed so as to implement a 6 F2 (6F*F) DRAM array. In particular, two neighboring access transistors are arranged, so that they have one common bit line contact. In addition, neighboring access transistors formed on a single active area line are electrically isolated from each other by an isolation gate line.
DE 199 28 781 C1 discloses a 6 F2 memory cell in which two adjacent memory cells share one common bit line contact. Two neighboring pairs of memory cells which are assigned to one active area line are separated and electrically isolated from each other by a groove which is filled with an isolating material.
Furthermore, U.S. Pat. No. 5,502,320, the disclosure of which is incorporated herein by reference in its entirety, discloses a memory cell array in which transistors are formed in continuous active area lines. The active area lines are arranged in parallel with the bit lines. Two adjacent pairs of neighboring memory cells are separated and isolated from each other by applying an appropriate voltage to isolation gate lines which are arranged between the two adjacent pairs of memory cells. The word lines and the isolation gate lines are implemented as buried word lines and buried isolation gate lines, respectively.